A bus is commonly employed to interconnect modules of a computer system and to transfer signals between them so that desired operations may be carried out by the system. One of the signals transferred between the modules is a clock signal used to control the timing of the desired operations. Specifically, the clock signal synchronizes the transmission and reception of data between the bus interface circuitry on each module.
For proper operation of the computer system, clock signals should arrive at the interface circuitry of the various modules at the same time; otherwise, reliable data transmission is not ensured. For example, if a module receiving data is "clocked" later than others, data placed on the bus by an earlier-clocked module may disappear before the receiving module has retrieved it from the bus. In order to avoid this problem, the data may be maintained on the bus long enough to ensure that even the late-clocked modules can receive it. However, the lack of simultaneity in reception of the clock signals at the modules, i.e., clock skew, directly impacts the performance of the synchronous computer. That is, the greater the skew, the longer the time required for each bus transfer in order to ensure proper reception of data transferred over the bus.
The amount of clock skew introduced into a computer system is a direct function of the variations in propagation delays among clock receiver chips of the system. These chips typically receive the clock signals and buffer, i.e., amplify, them. However, buffering of low-level signals with semiconductor chips to develop high-level digital pulse signals is very susceptible to propagation delay variations due to process, voltage, temperature and loading (PVTL) variations. Differences in propagation delay between clock "buffer" chips in a system directly translate into skew.
The problem of clock skew is addressed partly by employing a system clock source and distributing the clock signals to the respective modules. Distribution is accomplished in a manner such that the clock signals arrive essentially simultaneously at the modules. However, in each module the incoming clock signals must be processed, i.e., shaped, amplified and regenerated into multiple copies, before use by various circuits on the module. Such processing necessarily delays the signals; the delays can be expected to vary from module to module because of PVTL variations. These variations contribute significantly to clock skew, which must be reduced prior to further distribution of the clock signals.
One approach to reducing skew involves the use of an absolute delay regulator, which performs a precise measurement of the propagation delay of the clock signal in passing through the processing circuitry and then adjusts that delay so as to maintain a fixed-phase relationship between a non-processed input clock signal and the processed clock signal. An absolute delay regulator of this type is disclosed in patent application titled, METHOD AND APPARATUS FOR CLOCK SKEW REDUCTION THROUGH ABSOLUTE DELAY REGULATION, by Watson, Jr. et al. filed herewith, which application is expressly incorporated by reference as though fully set forth herein.
Specifically, the absolute delay regulator employs two delay adjusting units configured such that one adjusts an input clock signal by adding a desired amount of delay, while the other compensates for previously-measured propagation delays encountered by the input signal. The regulator then selects the updated clock signal from the proper delay unit and distributes it to circuitry external to the regulator. Thereafter, the roles of the delay adjusting units are switched and the regulator selects the updated clock signal from the other delay unit.
Selection of the updated clock signals is controlled by logic external to the processing circuitry. The logic thus generates a control signal that is asynchronous to the clock signals processed by the delay regulator. Timing problems may result from the lack of synchronization between the control and clock signals. The present invention is directed to the synchronization of the asynchronous control signal to the clock signals; in addition, the present invention enables distribution of the updated clock signal without interruption of system operation.
Therefore, it is among the objects of this invention to provide an arrangement for selecting an updated output clock signal from among various input clock signals without interrupting computer system operation.
Another object of the invention is to synchronize the clock signals with an asynchronous control signal having a phase that is different from that of the clock signals.
Yet another object of the present invention is to redistribute multiple copies of an updated, low-skew clock signals to circuitry on a module without disrupting the continuous flow of output clock signals.